1. Field of the Invention
The present invention relates to a semiconductor device provided with two kinds of transistors of different conduction types on an insulting layer.
2. Description of the Related Art
With shortening of gate length, the operation speed of a MOS (Metal Oxide Semiconductor) transistor is increasing. However, power consumption also increases, and a phenomenon that total performance of an integrated circuit becomes lower than that of an existing integrated circuit is conspicuous. The phenomenon is called the short channel effect. It is extremely important to suppress the effect as much as possible in order to realize a high-performance low-power-consumption integrated circuit. However, the short channel effect increases as the ratio of a transverse electric field to a vertical electric field increases. Consequently, when MOS transistors are formed in bulk silicon crystal, it is extremely difficult to suppress the short channel effect.
In recent years, attention is being paid to a technique of forming MOS transistors in a single-crystal silicon layer on an insulator layer (SOI (Silicon on Insulator) layer) (see Japanese Examined Patent Application Publication No. 2001-284596). In the technique, by thinning the SOI layer, the transverse electric field is made smaller. Further, by forming a high-concentration impurity layer just below the SOI layer and using the impurity layer as a back gate, the vertical electric field is increased. Therefore, it is said that the technique is very promising from the viewpoint of suppressing the short channel effect.